1. Field of the Invention
The present invention generally relates to voltage supplies for integrated circuits, and more particularly to switched-capacitor charge pumps used to power electronic memory structures such as dynamic random-access memory (DRAM).
2. Description of the Related Art
Power management has become a dominant concern in the development of data processing systems. Excess power usage is not only costly and inefficient, but also leads to heat management problems. These problems are particularly pronounced in computer systems having large amounts of memory. State of the art computer systems typically use dynamic random-access memory (DRAM) which is preferable over other memory structures such as static random-access memory (SRAM) because DRAM is more dense. However, DRAM can be more power intensive in circuit blocks for active power supply generation and refresh. SRAM uses a flip-flop memory cell but DRAM uses a capacitor-based memory cell which, due to current leakage, must be regularly refreshed. DRAM can consume a significant portion of a system's overall power.
Power management has become even more challenging with the advent of new memory technologies like embedded DRAM (eDRAM). This new design relies on the silicon-on-insulator (SOI) technology pioneered by International Business Machines Corp. using deep-trench capacitors. Deep-trench (3-dimensional) capacitors have a reduced footprint on the semiconductor substrate, and an eDRAM array has about one-third the area of a comparable DRAM array. Reducing the size of the memory makes it easier to embed the array on the same integrated circuit chip, e.g., a microprocessor or an application-specific integrated circuit (ASIC), to provide a system-on-a-chip solution. An exemplary commercial microprocessor might devote up to 60% of its surface area to memory. Replacing conventional DRAM with eDRAM cells allows the chip designer to build smaller chips and reduce the length of wire that data must travel as it commutes around the chip, resulting in the fastest memory access times ever recorded. Embedding memory further permits much wider buses and higher operation speeds and, due to the much higher density of eDRAM, larger amounts of memory can potentially be used.
An eDRAM array requires an on-chip power supply having precise high and low voltages (positive and negative) for the word lines that drive the rows of the memory array. The high voltage is used to activate a word line, and the low voltage is for standby. Various power supply designs can be used to deliver these voltages, including for example the Cockcroft-Walton voltage multiplier, the Dickson charge pump, and the Nakagome voltage doubler. The Cockcroft-Walton voltage multiplier uses a ladder network of capacitors and diodes or switches connected to a low voltage input. As a charge cascades through the capacitors it successively increases to finally yield a higher voltage at the output. The Dickson charge pump operates in a similar manner but in the Dickson design the nodes of the diode chain are coupled to the inputs via capacitors in parallel instead of in series. The Nakagome voltage doubler uses switched capacitors whose output nodes are connected to cross-coupled transistors
An advanced power supply based on the Nakagome design is described in the article “Switching Noise and Shoot-Through Current Reduction Techniques for Switched-Capacitor Voltage Doubler” by H. Lee and P. Mok, Journal of Solid-State Circuits vol. 40, n. 5, pp. 1136-1146 (May 2005), shown in FIG. 1. The voltage doubler 10 is driven by two-phase, non-overlapping clock signals produced by a clock phase generator 12 and two sets of inverter chains 14a, 14b. The clock signals control a first transistor pair 16a, 16b which charge and discharge the first capacitor 18, and a second transistor pair 20a, 20b which charge and discharge the second capacitor 22. The input terminals of transistors 16a and 20a are connected to the power supply voltage Vdd. A voltage booster circuit includes a pair of cross-coupled transistors 24a, 24b connected to the output nodes of capacitors 18 and 22 which provides automatic reverse bias of the junctions. The other terminals of transistors 24a and 24b are connected to the power supply voltage Vdd. Two serial transistors 26a, 26b in the booster circuit act as charge-transfer devices. The inputs and gates of transistors 26a, 26b are driven by respective level shifters 28a, 28b. Two additional transistors 30a, 30b are provided which increase the amount of transient current and thereby allow the serial power transistors 26a, 26b to be turned off faster. Two additional capacitors 32, 34 are connected in parallel with a resistor 36 between electrical ground and the input of transistor 30b for noise suppression. The common rail of transistor 26b, transistor 30b, capacitors 32, 34 and resistor 36 is the output Vpp of the voltage doubler.
While conventional charge pump designs such as that depicted in FIG. 1 achieve some efficiency by reducing no-load supply current dissipation, they still suffer from other inefficiencies relating to capacitive loading, voltage ripples, and peak current density. These inefficiencies can significantly affect power management in demanding applications such as eDRAM. It would, therefore, be desirable to devise an improved charge pump which could provide more efficient energy conversion with tight active and standby power control. It would be further advantageous if the improved charge pump could be provided in a more compact design.